A set associative, cache memory, of the type to which this invention relates is illustrated in the functional block diagram of FIG. 1, and also described in U.S. Pat. No. 7,054,184 assigned to the assignee of this invention, and incorporated herein by reference. The cache memory system shown in FIG. 1 is a four way, set associative cache memory system. The tag portion of the memory address is used to address the TAG Array RAM. The TAG array consists of 4-Way X 4 of SRAM data. Each of the addressable row in the TAG array represents 4 entries of the cache Set_ID, i.e., a total of 16 data bits per row, or 4 data bits per each 4-way. The TAG array could be 1K, 2K, or 4K . . . etc. deep (depending on the cache system implementation). The function of the bits is to identify the associativity set to be selected from the cache. In our example here, the cache is 4 way set associative, hence 4 bits are needed for the Set_ID field. Each bit corresponds to a set. Usually 1 and only 1 of the bits are ON, so that only 1 out of 4 sets is selected from the Cache Macro via the functional block labeled 4-to 1 late select in FIG. 1. As illustrated in FIG. 1, each of four multiplexers provides a 4-to-1 select function and the four combined provide the 16-to-4 select function whose four outputs comprise the Set-id (4) field.
FIG. 3 is a schematic diagram of a prior art dynamic 4-to-1 multiplexer of the type used in the prior art to generate one of the Set-id inputs to the Cache Macro late select function. It has a low active clock signal and includes four pull down transistor pairs. Each pair is comprised of a select transistor, here an N type Field Effect Transistor (NFET) with inputs (sel<0>, sel<1>, sel<2>. and sel<3>) and data transistor, another NFET with inputs (in <0>, in <1>, in <2>, and in <3>). Also illustrated here is an NFET pull down pair with inputs abist_sys_sel and abist_sys_in, which is used in a Built In Self Test mode of operation initiated by the test control logic. There is a 6th input labeled “lbist” which is an override signal supplied by the LBIST (Logic Built In Self Test) control logic. The lbist input is used to override the other inputs and force the multiplexer circuit to generate a selected output state.
An inverter connects the clock signal ck1 to the gates of PFET PRS1 and NFET NR. When the clock is in its standby high state, PRS1 turns on and NR turns off. During the clock standby state, PRS1 pre-charges node N by connecting it to a positive voltage source Vdd, pre-charging the node N high. Node N is connected to the multiplexer output “out_c”. A four transistor flip-flop coupled to the output maintains the state of the output out_c in either a logic high state or a logic low state until the potential on node N drops below or rises above the switching threshold of the flip-flop. The flip-flop transistors are constructed with small size devices, so that they could be over powered by the switching of node N during circuit restore or evaluation. When the clock signal falls to its low activate state, PRS1 turns off and NR turns on. Pre-charged node N stays high (being held high by the flip-flop latch. Select signals sel_0, sel_1, sel_2, or sel_3 turns on the evaluation NFETs. The sel_0 to sel_3 are orthogonal signals. In normal mode operation, only one, or none, of theses signals will be on (high), hence only one, or none, of the four NFET pairs will be active at a time. Which pair, if any, of the pull down pairs conducts depends on the content of the TAG Array RAM at the tag memory address. When both transistors of a pull down pair conduct, the pre-charged voltage at node N drops as the node discharges through the pull down pair and transistor NR to a sink, indicated as ground here. The output out_c on one of the four Set-ID lines drops, producing the leading edge of an output pulse on out_c. When the clock ck1 goes high, PRS1 turns on, NR turns off, the voltage on out_c rises, producing the trailing edge of the output pulse, and starting the recovery process for the next cache access.
It will be appreciated that the inputs to the multiplexer from the TAG Array RAM must be stable before the clock signal switches to its active state, and remain stable throughout the duration of the clock signal active state. The time allowed for the inputs to reach a stable state is known as the Set-up Time and the time during which the inputs must remain stable during the active state of the clock signal is known in the art as the Hold Time. In the prior art dynamic multiplexer of FIG. 3, the Set-up time, the Hold Time, and the width of the dynamic output pulse out_c are tied to one another. In the prior art, the multiplexer output pulse width is determined by the ck1 pulse width. A wide Set_ID pulse is needed in order to ensure proper and robust late select dynamic circuit operation at the cache. But an increase in the width of the ck1 clock pulse increases the hold time and a resultant degradation of cache performance.